Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs.
Marco WinzkerPeter PirschJochen ReimersPublished in: ISCAS (1995)
Keyphrases
- memory requirements
- memory space
- memory usage
- hierarchical architecture
- data flow
- computational complexity
- compression standards
- low memory
- international standard
- management system
- computational power
- real time
- multi layer
- multimedia
- computational speed
- software architecture
- reference model
- user friendly
- video sequences
- iso iec
- digital video
- image processing
- mpeg video
- network architecture
- coarse to fine
- hierarchical clustering