A High-Performance Error Concealment Processor for Video Decoder.
Shih-Chang HsiaShih Wen ChouPublished in: IWSOC (2005)
Keyphrases
- error concealment
- video decoder
- bitstream
- memory subsystem
- video quality
- video transmission
- coding scheme
- video codec
- bit rate
- low power consumption
- error resilience
- compression algorithm
- video coding
- macroblock
- single chip
- temporal error concealment
- packet loss
- visual quality
- motion vectors
- low cost
- ibm zenterprise
- frame rate
- rate distortion
- high speed
- power consumption
- wavelet coefficients
- low bit rate
- mobile devices
- real time
- reconstructed image
- optical flow
- feature extraction
- image sequences