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A Low Power Miller Compensation Technique for Two Stage Op-amp in 65nm CMOS Technology.
Rajasekhar Nagulapalli
Khaled Hayatleh
Steve Barker
B. Naresh Kumar Reddy
B. Seetharamulu
Published in:
ICCCNT (2019)
Keyphrases
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cmos technology
low power
low cost
power consumption
high speed
low voltage
single chip
power dissipation
mixed signal
silicon on insulator
digital signal processing
image sensor
low power consumption
digital images
image processing
nm technology
real time
pattern recognition
cmos image sensor