Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator.
Yifan QianChang MengYawen ZhangWeikang QianRunsheng WangRu HuangPublished in: ISCAS (2021)
Keyphrases
- low power
- logic synthesis
- logic circuits
- neural network
- power consumption
- high speed
- low cost
- single chip
- multi valued
- gate array
- vlsi architecture
- inductive learning
- digital signal processing
- parallel implementation
- heuristic search
- low power consumption
- power dissipation
- cmos technology
- mixed signal
- vlsi circuits
- real time
- parallel algorithm
- sensor networks
- power reduction
- pattern recognition
- machine learning
- ultra low power