Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution.
Vijay SundararajanKeshab K. ParhiPublished in: ARVLSI (1999)
Keyphrases
- low power
- cmos technology
- logic circuits
- power consumption
- high speed
- low cost
- nm technology
- power dissipation
- low voltage
- single chip
- wireless transmission
- vlsi circuits
- gate array
- high power
- vlsi architecture
- low power consumption
- power reduction
- mixed signal
- digital signal processing
- compressed images
- image sensor
- delay insensitive