Hardware implementation of a background substraction algorithm in FPGA-based platforms.
Elisa Calvo-GallegoSantiago Sánchez-SolanoPiedad Brox JiménezPublished in: ICIT (2015)
Keyphrases
- hardware implementation
- image processing algorithms
- fpga implementation
- efficient implementation
- pipeline architecture
- signal processing
- optimal solution
- hardware architecture
- np hard
- computational complexity
- k means
- learning algorithm
- real time
- fractal encoding
- image binarization
- detection algorithm
- data mining
- hardware design
- parallel architecture
- parallel implementation
- neural network
- tree structure
- fpga technology
- expectation maximization