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Design and implementation of an FPGA based processor for compressed images (poster abstract).

V. S. BalakrishnanHardy J. PottingerFikret ErçalMukesh Agarwal
Published in: FPGA (2000)
Keyphrases
  • compressed images
  • hardware architecture
  • hardware design
  • image segmentation
  • signal processing
  • hardware implementation
  • feature extraction
  • high speed
  • embedded systems
  • artifact reduction