An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding.
Jianying PengXing QinDexian LiXiaolang YanXiexiong ChenPublished in: ASAP (2007)
Keyphrases
- video coding
- single instruction multiple data
- processing elements
- processor array
- massively parallel
- motion estimation
- rate distortion
- bit rate
- motion compensation
- motion compensated
- level parallelism
- video compression
- parallel implementation
- parallel processing
- video codec
- real time
- high definition
- parallel computers
- video quality
- motion vectors
- motion compensated prediction
- macroblock
- motion estimation and compensation
- rate control
- image and video compression
- error resilience
- parallel algorithm
- associative memory
- scalable video coding
- random access
- hardware architecture
- compression efficiency
- video coder
- object based coding
- bitstream
- inter frame
- shared memory
- optical flow
- block based motion estimation
- video decoder
- video encoder
- low bit rate