A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup.
Carsten BieserMartin BahlingerMatthias HeinzChristian StopsKlaus D. Müller-GlaserPublished in: FPL (2006)
Keyphrases
- bitstream
- xilinx virtex
- hardware architecture
- hardware implementation
- field programmable gate array
- coding scheme
- bit rate
- compression algorithm
- scalable video coding
- video quality
- scalable video
- video transmission
- error resilience
- bit plane
- image processing algorithms
- signal processing
- pattern recognition
- frame rate
- rate distortion
- base layer
- bit planes
- image sequences
- error concealment
- design methodology
- application specific
- embedded systems
- video coding
- wavelet coefficients