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A 40nm area-efficient Effective-bit-combination-based DNN accelerator with the reconfigurable multiplier.

Yanghan ZhengZhaofang LiKaihang SunKuan-Pei LeeKea-Tiong Tang
Published in: AICAS (2023)
Keyphrases
  • hardware implementation
  • bit vector
  • computationally expensive
  • neural network
  • low cost
  • computationally efficient
  • cost effective
  • highly efficient
  • bit wise
  • genetic algorithm