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A 5-13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process.
Zhou Shu
Shalin Huang
Zhipeng Li
Peng Yin
Jiandong Zang
Dongbing Fu
Fang Tang
Amine Bermak
Published in:
IEEE Trans. Circuits Syst. (2020)
Keyphrases
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wide range
high speed
packet loss
data sets
website
digital images