Low power driven loop tiling for RRAM crossbar-based CNN.

Yuanhui Ni Keni Qiu Weiwen Chen Lixue Xia Yu Wang

Published in: SAC (2018)

Keyphrases

low power
power consumption
low cost
high speed
cellular neural networks
single chip
digital signal processing
high power
low power consumption
cmos technology
logic circuits
wireless transmission
vlsi architecture
real time
vlsi circuits
gate array
delay insensitive
power saving