Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec.

Lijun Gao Keshab K. Parhi

Published in: ISCAS (4) (2001)

Keyphrases

low power
low latency
high speed
vlsi design
low cost
power consumption
highly efficient
real time
object oriented
rate distortion
data acquisition
frame rate
design methodology