Self-Timed Architecture of a Reduced Instruction Set Computer.
Ilana DavidRan GinosarMichael YoeliPublished in: Asynchronous Design Methodologies (1993)
Keyphrases
- instruction set
- computer architecture
- floating point
- application specific
- level parallelism
- embedded systems
- dedicated hardware
- memory subsystem
- computer systems
- real time
- instruction set architecture
- artificial intelligence
- parallel computing
- low power
- multi dimensional
- general purpose
- database systems
- information systems
- database