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A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O.
William Y. Li
Hyung Seok Kim
Kailash Chandrashekar
Khoa Minh Nguyen
Ashoke Ravi
Published in:
ISLPED (2017)
Keyphrases
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high speed
input output
low cost
power consumption
low power
general purpose
reconfigurable architecture