TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual Caches.
Binh PhamDerek HowerAbhishek BhattacharjeeTrey CainPublished in: IEEE Comput. Archit. Lett. (2018)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- single chip
- data center
- wireless transmission
- vlsi circuits
- cache misses
- high power
- image sensor
- digital signal processing
- gate array
- logic circuits
- image processing
- hardware and software
- low power consumption
- power reduction
- real time
- cmos technology
- power dissipation
- vlsi architecture
- low complexity
- signal processing