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A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications.
A. V. AnanthaLakshmi
Gnanou Florence Sudha
Published in:
Microprocess. Microsystems (2017)
Keyphrases
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digital signal processing
data flow
floating point arithmetic
signal processing
floating point
processing units
real time
computer vision
information systems
image processing
computer science
efficient implementation
low power
computer vision and image processing
power dissipation