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Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices.

Andrea SilvagniStefano ZanardiAlessandro ManstrettaMarco ScottiLuca CrippaGiancarlo RagoneGiuseppe FusilloGiovanni CampardoOsama KhouriMarcello Stefanelli
Published in: ICECS (2001)
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