ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers.
Christoffer FougstedtOscar GustafssonCheolyong BaeErik BörjesonPer Larsson-EdeforsPublished in: OFC (2020)
Keyphrases
- data center
- design methodology
- high speed
- design process
- power consumption
- digital signal processing
- circuit design
- single chip
- cloud computing
- hardware architecture
- energy efficiency
- digital signal processor
- power management
- mission critical
- integrated circuit
- user experience
- cost effective
- energy consumption
- signal processing