An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering.
Félix TobajasGustavo Marrero CallicóPedro A. PérezValentin de ArmasRoberto SarmientoPublished in: IEEE Trans. Consumer Electron. (2008)
Keyphrases
- hardware architecture
- deblocking filter
- adaptive filtering
- low power
- hardware implementation
- blocking artifacts
- filtering algorithm
- low bit rate
- bilateral filtering
- filtering process
- hardware architectures
- compressed video sequences
- filtering method
- video communication
- discrete cosine transform
- median filter
- spatial domain
- power consumption
- computational complexity
- compressed images
- field programmable gate array
- image quality
- video coding standard
- real time
- signal processing
- bit rate
- video coding
- motion compensation
- rate control
- embedded systems
- transform domain