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Design of low-voltage CMOS pipelined ADCs using 1 pico-Joule of energy per conversion.

Bruno VazNuno F. PaulinoJoão GoesR. CostaRomero TavaresAdolfo Steiger-Garção
Published in: ISCAS (1) (2002)
Keyphrases
  • low voltage
  • design considerations
  • cmos technology
  • case study
  • design methodology
  • real time
  • computer vision
  • user interface
  • design process
  • power consumption
  • energy efficiency
  • power line