A 1.6-GHz CMOS PLL with on-chip loop filter.
James F. ParkerDaniel RayPublished in: IEEE J. Solid State Circuits (1998)
Keyphrases
- high speed
- analog vlsi
- loop filter
- low power
- deblocking filter
- cmos image sensor
- circuit design
- single chip
- motion estimation and compensation
- motion compensated
- focal plane
- low cost
- power consumption
- cmos technology
- chip design
- clock frequency
- random access memory
- frame rate
- video coding
- image sensor
- power dissipation
- ultra low power
- motion compensation
- nm technology
- real time
- dynamic range
- motion estimation
- delay insensitive
- metal oxide semiconductor
- intra prediction
- coding efficiency
- residual signal