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Power efficient low latency architecture for decoder: Breaking the ACS bottleneck.

Subramanyam RadhaDavid Sundararaj ShyluPerattur Nagabushanam
Published in: Int. J. Circuit Theory Appl. (2019)
Keyphrases
  • low latency
  • real time
  • highly efficient
  • high speed
  • high throughput
  • high bandwidth
  • cost effective
  • virtual machine
  • data sets
  • databases
  • data streams
  • response time
  • data collection
  • stream processing