Stateless Model Checking Under a Reads-Value-From Equivalence.
Pratyush AgarwalKrishnendu ChatterjeeShreya PathakAndreas PavlogiannisViktor TomanPublished in: CAV (1) (2021)
Keyphrases
- model checking
- temporal logic
- model checker
- automated verification
- formal verification
- partial order reduction
- finite state
- formal specification
- temporal properties
- symbolic model checking
- transition systems
- verification method
- formal methods
- finite state machines
- concurrent systems
- process algebra
- timed automata
- epistemic logic
- computation tree logic
- pspace complete
- asynchronous circuits
- reachability analysis
- search algorithm
- artificial intelligence