A low power merge cell processor for real-time spike sorting in implantable neural prostheses.
Michael D. LindermanTeresa H. MengPublished in: ISCAS (2006)
Keyphrases
- low power
- cell processor
- low cost
- high speed
- real time
- power consumption
- vlsi architecture
- low power consumption
- signal processor
- wireless transmission
- high power
- single chip
- digital signal processing
- spike trains
- network architecture
- vlsi circuits
- logic circuits
- image sensor
- gate array
- lookup tables
- high definition television
- delay insensitive
- spiking neurons
- signal processing
- image processing
- mixed signal
- power reduction
- cmos technology
- digital camera