A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques.
Nele ReyndersWim DehaenePublished in: A-SSCC (2011)
Keyphrases
- cmos technology
- power dissipation
- nm technology
- low power
- power consumption
- data flow
- low voltage
- logic circuits
- high speed
- digital signal processing
- silicon on insulator
- chip design
- low cost
- power reduction
- flip flops
- design methodology
- vlsi circuits
- single chip
- power management
- image sensor
- neural network
- finite state machines
- computational complexity