Hardware Implementation of Successive-Cancellation Decoders for Polar Codes.
Camille LerouxAlexandre J. RaymondGabi SarkisIdo TalAlexander VardyWarren J. GrossPublished in: J. Signal Process. Syst. (2012)
Keyphrases
- hardware implementation
- decoding algorithm
- signal processing
- efficient implementation
- software implementation
- image processing algorithms
- fourier transform
- error correction
- fpga implementation
- dedicated hardware
- field programmable gate array
- rotation invariant
- frequency domain
- hardware architecture
- hardware design
- polar coordinates
- pipeline architecture
- memory management
- fpga technology
- parallel architecture