A CMOS power line communication for EEG.
Paulo Marcos PintoTales Cleber PimentaRobson Luiz MorenoPublished in: ICM (2016)
Keyphrases
- power line communication
- power line
- low voltage
- electric power
- eeg signals
- high speed
- test bed
- brain computer interface
- low cost
- circuit design
- motor imagery
- event related
- power consumption
- brain activity
- analog vlsi
- low power
- design considerations
- power supply
- power management
- signal processing
- cmos technology
- neural network
- frequency band
- image processing
- event related potentials
- genetic algorithm