A New Move Toward Parallel Assay Operations in a Restricted Sized Chip in Digital Microfluidics.
Debasis DhalArpan ChakrabartyPiyali DattaRajat Kumar PalPublished in: ACSS (2) (2014)
Keyphrases
- parallel processing
- circuit design
- floating point arithmetic
- cmos image sensor
- mixed signal
- level parallelism
- low cost
- parallel implementation
- massively parallel
- computer architecture
- shared memory
- ibm sp
- high speed
- real time
- processing units
- multithreading
- low power
- distributed memory
- physical design
- small sized
- analog vlsi
- phase locked loop