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Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel Leakage of AES Circuits.
Yuto Miura
Hiroki Nishikawa
Xiangbo Kong
Hiroyuki Tomiyama
Published in:
ICEIC (2024)
Keyphrases
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clock frequency
power consumption
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power dissipation
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parallel architecture
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information systems
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