Design of Heterogeneous Reconfigurable Cipher Engine Basing on FPGA+ASIC.
Guangcai CuiTao MengYijuan ShiHaojuan ChenPublished in: BigCom (2019)
Keyphrases
- hardware implementation
- hardware architecture
- low cost
- design methodology
- single chip
- hardware design
- user interface
- field programmable gate array
- case study
- design process
- circuit design
- xilinx virtex
- real time
- high speed
- software architecture
- general purpose
- fpga implementation
- low power consumption
- hw sw
- neural network