Low-Power HEVC 1-D IDCT Hardware Architecture.

Luciano A. Braatz Daniel Palomino Luciano Volcan Agostini Bruno Zatt Marcelo Schiavon Porto

Published in: SBCCI (2018)

Keyphrases

low power
hardware architecture
power consumption
high speed
low cost
hardware implementation
single chip
low power consumption
video codec
video compression
low complexity
associative memory
field programmable gate array
frame rate
parallel processing
motion compensated
image processing
real time