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High performance architecture for the encoder of JPEG-LS on SOPC platform.

Lih-Jen KauShih-Wei Lin
Published in: SiPS (2013)
Keyphrases
  • reconfigurable hardware
  • lossless compression
  • image processing
  • high quality
  • jpeg ls
  • rate distortion
  • low complexity
  • compression scheme
  • hardware implementation
  • video compression
  • video codec