H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture.
Adam MajorYing YiIoannis NousiasMark MilwardSami KhawamTughrul ArslanPublished in: SoCC (2006)
Keyphrases
- instruction set
- layered architecture
- fpga implementation
- efficient implementation
- hardware implementation
- architectural design
- multimedia
- software implementation
- parallel architecture
- implementation details
- hardware architecture
- core components
- video codec
- floating point
- level parallelism
- real time
- management system
- java platform
- platform independent
- hardware design
- design methodology
- instructional design
- software architecture
- video coding