14.5 fJ/conversion-step 9-bit 100-kS/s non-binary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS.
Jagadish Dasarahalli NarasimaiahMujoor Shankaranarayana BhatPublished in: IET Circuits Devices Syst. (2018)
Keyphrases
- energy efficient
- non binary
- analog to digital converter
- random access memory
- binary representation
- wireless sensor networks
- constraint satisfaction problems
- energy consumption
- sensor networks
- energy efficiency
- power consumption
- power supply
- image sensor
- nm technology
- base station
- cmos technology
- routing protocol
- high speed
- mixed signal
- data transmission
- low power
- constraint satisfaction
- low cost
- image processing algorithms
- data sets
- multi channel
- low voltage
- cmos image sensor
- response time
- silicon on insulator