Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC.
Ari KulmalaOlli LehtorantaTimo D. HämäläinenMarko HännikäinenPublished in: EURASIP J. Embed. Syst. (2006)
Keyphrases
- mpeg standard
- power reduction
- low power
- enhancement layer
- video decoder
- video codec
- multiprocessor architecture
- high speed
- mpeg avc
- field programmable gate array
- rate distortion
- video transcoding
- bit rate
- scalable video coding
- embedded systems
- low cost
- video coder
- base layer
- power consumption
- multimedia content
- low power consumption
- digital video
- video compression
- hardware implementation
- hardware software co design
- variable bit rate
- bitstream
- multimedia
- multiprocessor systems
- video coding
- single chip
- hardware design
- video coding standard
- real time
- video quality
- hardware and software
- low complexity
- visual descriptors
- level parallelism
- signal processing