Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two.

Stephan Held Sophie Theresa Spirkl

Published in: ACM Trans. Algorithms (2018)

Keyphrases

logic circuits
sample size
shift register
support vector
multi class
depth information
power dissipation
bayesian networks
multiscale
high speed
transfer function
linear constraints
circuit design
random number generator
high level synthesis