Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA.

Ren Chen Sruja Siriyal Viktor K. Prasanna

Published in: FPGA (2015)

Keyphrases

memory efficient
external memory
energy consumption
hardware design
low cost
energy minimization
hardware implementation
iterative deepening
field programmable gate array
multiple sequence alignment
low energy
real time
signal processing
real time image processing
parallel hardware
energy saving
data structure