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A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner.
Joo-Hyung Chae
Hyeongjun Ko
Jihwan Park
Suhwan Kim
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2019)
Keyphrases
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high speed
power consumption
multiscale
video streams
database
learning algorithm
training phase
learning phase
power supply
multiple input multiple output