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A 1.1mW 200kS/s incremental ΔΣ ADC with a DR of 91.5dB using integrator slicing for dynamic power reduction.
Patrick Vogelmann
Michael Haas
Maurits Ortmanns
Published in:
ISSCC (2018)
Keyphrases
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power consumption
power reduction
power saving
low power
pattern recognition
energy efficiency
design methodology
power dissipation