DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs.
Jacob T. GrycelRobert J. WallsPublished in: CoRR (2019)
Keyphrases
- field programmable gate array
- hardware implementation
- hardware software
- hardware architecture
- hardware design
- real time
- parallel architectures
- fpga technology
- hardware and software
- embedded systems
- low cost
- reconfigurable hardware
- management system
- fpga implementation
- efficient implementation
- software implementation
- vlsi implementation
- hardware architectures
- host computer
- massively parallel
- lightweight
- computer systems