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High-level co-simulation based on the extension of processor simulators.
S. K. Tsasakou
Nikos S. Voros
Alexios N. Birbas
M. V. Koziotis
D. G. Papadopoulos
Published in:
J. Syst. Archit. (2001)
Keyphrases
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high level
low level
high speed
higher level
parallel processing
learning algorithm
single chip
database
genetic algorithm
programming language
efficient implementation
mid level
intermediate level
multiprocessor systems