Design and implementation of an 11-bit 50-MS/s split SAR ADC in 65 nm CMOS.

Anh Trong Huynh Hoa Thai Duong Hoang Viet Le Efstratios Skafidas

Published in: ISCAS (2014)

Keyphrases

analog to digital converter
circuit design
cmos technology
efficient implementation
nm technology
power consumption
low power
design methodology
design considerations
single chip
high speed
design process
real time
image reconstruction
implementation issues
mixed signal