Login / Signup
multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers.
Leandro Zafalon Pieper
Eduardo A. C. da Costa
José C. Monteiro
Published in:
SBCCI (2013)
Keyphrases
</>
design considerations
engineering design
programmable logic
artificial intelligence
design process
cost effective
design principles
hardware implementation
design decisions