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A recursive technique for computing delays in series-parallel MOS transistor circuits.
Jean Paul Caisso
Eduard Cerny
Nicholas C. Rumin
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1991)
Keyphrases
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series parallel
floating gate
high speed
temporal reasoning
precedence constraints
power dissipation
circuit design
integrated circuit
low power
image sequences
constraint networks
tree decomposition