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Low power nanoscale buffer management for network on chip routers.
Suman Kalyan Mandal
Ron Denton
Saraju P. Mohanty
Rabi N. Mahapatra
Published in:
ACM Great Lakes Symposium on VLSI (2010)
Keyphrases
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buffer management
low power
high speed
power dissipation
cmos technology
power consumption
low cost
single chip
end to end
digital signal processing
flash memory
load balancing
network management
real time
routing algorithm
storage devices
random access
image sensor
sensor networks