Gate-level modeling for CMOS circuit simulation with ultimate FinFETs.
Nicolas ChevillonMorgan MadecChristophe LallementPublished in: NANOARCH (2012)
Keyphrases
- cmos technology
- high speed
- analog vlsi
- circuit design
- discrete event simulation
- low power
- low voltage
- low cost
- metal oxide semiconductor
- chip design
- delay insensitive
- nm technology
- simulation environment
- simulation model
- parallel processing
- simulation models
- mathematical models
- simulation study
- power consumption
- mathematical model
- higher level
- control system