Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System.
Keqin LiVictor Y. PanPublished in: IPPS/SPDP (1999)
Keyphrases
- linear array
- matrix multiplication
- distributed memory
- processing elements
- parallel computers
- hardware implementation
- shared memory
- message passing
- parallel architecture
- parallel implementation
- high speed
- low cost
- image processing algorithms
- parallel computing
- field programmable gate array
- parallel processing
- parallel processors
- general purpose
- associative memory
- massively parallel
- matrix factorization
- neural network
- software development