A highly parallel SAD architecture for motion estimation in HEVC encoder.
Ahmed MedhatAhmed ShalabyMohammed Sharaf SayedMaha ElsabroutyFarhad MehdipourPublished in: APCCAS (2014)
Keyphrases
- motion estimation
- highly parallel
- motion vectors
- video compression
- video codec
- low complexity
- video coding
- motion compensation
- motion compensated
- rate distortion
- inter frame
- macroblock
- reference frame
- bit rate
- coding efficiency
- parallel architectures
- video coding standard
- efficient implementation
- optical flow
- video sequences
- computing systems
- single pass
- software architecture
- single chip
- real time
- image sequences
- computer vision
- computational complexity
- parallel programming
- super resolution
- general purpose
- parallel computers