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Packet Processing acceleration with a 3-stage programmable pipeline engine.
Ioannis Papaefstathiou
Kyriakos Vlachos
Nikos A. Nikolaou
Nicholas Zervos
Victor B. Lawrence
Published in:
IEEE Commun. Lett. (2004)
Keyphrases
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processing pipeline
real time
data processing
parallel architecture
data sets
low cost
digital signal processors
general purpose
end to end
single chip